EPROM and like memory devices or cells and various methods of manufacturing these devices are well known in the art. An example of one such prior art EPROM device is illustrated in FIG. 1 and generally designated by the reference numeral 10. As depicted in FIG. 1, this device includes a silicon substrate 12 having implanted therein a source S and a drain D on opposite sides of a channel C which, along with the source and drain, form a transistor region of the EPROM device. A gate oxide 14 coats the top surface of silicon substrate 12 and serves to support an array of different layers directly over the channel C, as illustrated in FIG. 1. This array of different layers includes a lower most or first film layer 16, such as a doped polycrystalline silicon (polysilicon or poly I) layer which serves as a floating gate. The terms first film layer and poly I will be used interchangeably hereinafter. A film layer in the manufacture of a memory cell is also any other suitable material, for example, doped amorphous silicon, may also be "polycide", for example tungsten silicide layer over doped polysilicon, and is not limited to polysilicon. On top of the poly I layer 16 are two additional oxide layers 18 and 20 with a nitride layer 22 therebetween (ONO layers), or an alternative can be any other dielectric layer such as tantalum part oxide, and finally an uppermost or second film layer 24 or other suitable material such as doped polycrystalline silicon (polysilicon or poly II) layer 24 which serves as a control gate. The terms second film layer and poly II will be used interchangeably hereinafter. The ONO layers serve to insulate the poly land II layers from one another.
The EPROM device shown in FIG. 1 is but one of a relatively large number of such memory devices which together form an arrangement 26 of such devices sharing a common oxide coated silicon substrate, as illustrated in FIG. 2. As seen there, four such devices 10 are depicted on common oxide coated substrate 12. While not shown in FIG. 2, each of these devices is comprised of its own transistor region including a source, drain and channel and its own associated array of different layers including a poly I layer, a poly II layer and ONO layers therebetween. Also not shown in FIG. 2 are the standard electrical connections between the individual memory cell devices 10, which are referred to as second film layers 25 (see FIG. 4). Furthermore, for purposes of clarity, the various components making up the different memory devices are not illustrated in FIG. 2. It should be noted, however, that the various memory devices are arranged in rows 11 and columns 13 with row spaces R1, R2 and so on and column spaces C1, C2 and so on separating the individual memory devices from one another. Furthermore, the terms columns and rows can be used oppositely from the manner is which they are used in the description of the present invention, and that this invention is not dependent upon the terms and the labeling of rows and columns.
Having described the arrangement 26 of EPROM devices 10 from a structural standpoint, attention is now directed to one way in which the arrangement is produced in accordance with the prior art. To this end, attention is first directed to FIG. 3 which illustrates the overall arrangement of an EPROM device at an early stage in its formation. Specifically, the gate oxide layer 14 has been laid down on the top surface of a silicon or other type of semiconductor substrate 12. In addition, a first film layer 16 such as poly land ONO layers 22 have been formed over the oxide coated substrate. FIG. 3 depicts that sections of the ONO and poly I layers have been etched away by conventional lithography to form a series of columns 13 of different layers separated by column spaces C1, C2 and so on, such between opposing sidewalls 28 of adjacent columns 13. Thus far, no row spaces R1, R2 and so on have been provided and, therefore, each columns 13 is continuous along its entire length.
Turning to FIG. 4, after column spaces C1, C2 and so on, have been formed and after source/drain regions associated with the various EPROM devices are established within the substrate, at least one thick layer of differential oxide 34 is grown wherever the first film layer is exposed, specifically along the first film layer segments of sidewalls 28 (see FIG. 1) and over the exposed gate oxide layer 14 within the column spaces. These differential oxide layers, which are generally indicated at 34 in FIG. 4 serve to physically and chemically protect the source and drain region during further processing of the overall arrangement of EPROM device and specifically during the formation of row spaces R1, R2 and so on.
After the formation of differential oxide layer 34, a second film layer 24 such as a polysilicon II layer is formed over the entire unit 26, that is, over the differential oxide layer 34 and over the ONO regions which were not covered by the differential oxide layer 34.
After the second film layer 24 is laid down, photoresist 30 is lithographically patterned in rows 11 of the unit 26, the rows 11, of course, parallel to the spaces defined by row spaces R1, R2, and so on. In other words, there is no resist remaining in the spaces defined by row spaces R1, R2, and so on. Accordingly, during the etching process, the goal is to remove the second film layer and the ONO and first film layer, where present, from the spaces defined by the row spaces R1, R2, and so on.
A serious drawback in the overall formation process described thus far resides in the formation of the relatively thick differential oxide 34. To illustrate the drawback, FIG. 5 shows a cross section denoted as X in FIG. 4 of the layers laid down in the region which will, after etching, provide the spaces defined by the row spaces, R1, R2, and so on. In particular, as illustrated in FIG. 5, because of its thickness and its failure to form adjacent to the ONO layers, 18, 20, 22, the differential oxide 34 has been found to penetrate significantly into the sidewalls 28 of the columns 13 at the tops of their respective first film layers 16, thereby forming what may be referred to as overhanging wedges 36. The significance of these overhanging wedges 36 will become apparent below.
Columns 13 are separated into individual EPROM devices 10, as illustrated in FIG. 2, which is representative of, but does not include, all elements of an operable EPROM with second film layer 25 (not shown in FIG. 2 but shown in FIG. 4) positioned across the ONO poly I island and in a continuous manner therebetween. 0f particular interest is the way in which the first and second film layers, 16 and 24 respectively, as shown in FIG. 5, are removed from the areas which, after etching, are defined by row spaces R1, R2, and so on.
In the prior art, removal of both the first and second film layers 16 and 24 is done by means of vertical etching which is preferable in most processing applications. The differential oxide layer 34, which is electrically inert, is not entirely removed by plasma etching and therefore, its skeleton, as depicted in FIGS. 7 and 8, is left extending across row spaces, R1, R2 and so on as shown by cross-sectional area X of FIG. 6, after all etching has taken place. However, note specifically from FIG. 7 (which shows a cross-sectional view taken along cross-section X shown in FIG. 6) that, as a result of this vertical etching process, remnants 42 from the poly I material from first film layer 16 are formed on the inside of the portions of differential oxide 34 because they are located under the overhanging wedges 36 of differential oxide and are not entirely removed during the vertical etching process. Since the vertical etching process etches oxide slowly, the oxide "masks" the underlying poly I layer protecting it from etching. Furthermore, as a result of this vertical etching process, remnants 44 from the poly II material from second film layer 24 are formed in the outside portions of differential oxide 34 because they are not removed during the vertical etching process due to masking by the oxide. That is, there are remnants 42 and 44 of both the poly I and poly II, respectively, which are left in the inside and on the outside of the differential oxide 34 because they are not removed by vertical etching. These unremoved polysilicon remnants tend to form stringers across row spaces R1, R2 and so on between adjacent EPROM devices 10. These polysilicon stringers, which lie generally in the region indicated by cross-section X in FIG. 6, if left in place, will short the EPROM devices 10 together making the devices inoperative.